Memory devices provide data storage for electronic systems. One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that may be erased and reprogrammed in blocks. Many modern personal computers have BIOS stored on a flash memory chip. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of non-volatile memory cells arranged in row and column fashion. The cells are usually grouped into blocks. Each of the cells within a block may be electrically programmed by charging a charge storage region. The charge may be removed from the charge storage region by a block erase operation. Data is stored in a cell as charge in the charge storage region.
NAND is a basic architecture of flash memory. A NAND cell unit comprises at least one select gate coupled in series to a serial combination of memory cells (with the serial combination being commonly referred to as a NAND string). The gates of the NAND string have traditionally been single level cells (SLCs), but manufacturers are transitioning to utilization of multilevel cells (MLCs) for gates of NAND strings. An SLC stores only one data bit, whereas an MLC stores multiple data bits. Accordingly, memory can be at least doubled by transitioning from SLCs to MLCs.
Charge has traditionally been stored within flash memory in a floating gate. The floating gate may comprise, for example, conductively-doped silicon. Recently, interest has developed in utilizing charge-trapping materials to store charge. The charge-trapping materials may be layers (such as layers of silicon nitride) that have charge-trapping centers therein, or may be discrete islands that individually function as charge-trapping centers.
Of particular interest is the utilization of nanoparticles as charge-trapping centers; with nanoparticles being understood to be structures less than or equal to about 1000 nanometers along a maximal cross-section, and frequently less than 10 nanometers, or even less than 3 nanometers along a cross-section. In some applications, the nanoparticles may have maximal cross-sectional dimensions of from about 1 nanometer to about 100 nanometers. The nanoparticles may be configured to trap less than or equal to about 20 charges, and may, for example, be configured to trap from about one charge to about 20 charges. The nanoparticles may be substantially spherical, and the substantially spherical nanoparticles may be referred to as nanodots.
The nanoparticles may have any of numerous compositions, and may, for example, comprise, consist essentially of, or consist of one or more of Au, Ag, Co, Ge, Ir, Ni, Pd, Pt, Re, Ru, Si, Ta, Te, Ti and W.
The amount of charge stored on individual nanoparticles may depend on the size and composition of the nanoparticles.
Problems with the utilization of nanoparticles occur in obtaining uniform distribution of nanoparticles (i.e., a uniform population density of the nanoparticles as expressed in nanoparticles per unit area), and uniform size of the nanoparticles. If there is too much variation in distribution and/or size of the nanoparticles, then there may be excessive variation in cell-to-cell performance parameters. Variation in cell-to-cell performance may be particularly problematic for MLC-type devices.
It is desired to develop fabrication processes which alleviate or overcome one or more of the above-discussed difficulties.